The present invention relates to a semiconductor device having a semiconductor substrate having a trench such as a trench capacitor formed on its surface and a manufacturing method thereof.
In recent years, Large Scale Integrated Circuits (LSIs) are widely used in the important parts of computers and communications equipment. Due to this, the performance of the overall system is closely related to the performance of an LSI itself. The improvement in the performance of the single LSI can be realized by improving integration, that is, making elements smaller.
Various problems, however, arise as elements are smaller. In case of a capacitor of a DRAM memory cell, for example, if the area of the capacitor is smaller, its capacity tends to decrease. As a result, software-related errors occur such as the content of memory is erroneously read or the storage content is destroyed by the a line.
As one of the capacitors effective for solving, these problems, there is known a trench capacitor. The trench capacitor is intended to ensure necessary capacity by making use of the sides of a trench for the capacitor area.
The trench capacitor has been conventionally formed as follows.
Using photolithography and Reactive Ion Etching (to be referred to as RIE hereinafter), a trench is formed on a silicon substrate. After an arsenic doped glass film is deposited thereon, the arsenic within the arsenic doped glass film is diffused into the surface of the trench by solid phase diffusion and an impurity diffused layer of high impurity concentration which serves as a capacitor electrode (or plate electrode) is formed on the surface of the trench.
Lastly, after forming a capacitor insulating film on the surface of the trench, an arsenic doped amorphous silicon film which serves as a storage node is deposited, whereby the trench capacitor is completed.
The conventional formation method as stated above, however, has the following problems.
If using the RIE, a tapered trench is formed and the embedding shape of the storage node (which is the arsenic doped amorphous silicon film) tends to deteriorate. The deterioration in the embedding shape becomes more obvious if the diameter of the trench is smaller. This makes it difficult to provide smaller elements.
In addition, as a result of the RIE during the trench formation, the surface of the trench becomes uneven and the electric field concentrates on the uneven portions, thereby disadvantageously decreasing the withstand voltage of the insulating film of the capacitor.
To solve the latter problem, it is proposed the surface of the trench is smoothed by means of Chemical Dry Etching (to be referred to as CDE hereinafter). If a collar oxide film is formed on the upper wall of the trench, the collar oxide film needs to be formed thick by a degree corresponding to that etched by the CDE due to the fact that large etching selectivity between the collar oxide film and the silicon substrate is not expected.
It is however difficult to form a thicker collar oxide film on the upper wall of the trench whose diameter has become narrower as the sizes of the elements including the trench have become smaller. For that reason, the above-stated CDE is not suitable for and inapplicable to the smaller-sized elements.
Furthermore, if an exposure mask of a rectangular pattern is used as an exposure make for trench formation to realize high density elements, then a trench having angular portions with a small radius of curvature is formed and the electric field concentrates on that angular portions with small radius of curvature. As a result, the withstand voltage of the capacitor insulating film disadvantageously deteriorates.
Moreover, if the diameter of the trench is smaller and smaller, the thickness of the arsenic doped glass film which is the source of the solid phase diffusion cannot be ensured in a sufficient way. As a result, it is difficult to form an impurity diffused layer of high impurity concentration on the surface of the trench.
If the arsenic doped glass film is deposited deep enough to embed the trench therewith to ensure the above-stated film thickness of the arsenic doped glass film, the impurity diffused layer of high impurity concentration is not necessarily formed. If formed, this causes the problem that it is difficult to peel off the arsenic doped glass in the later step.
If the diameter of the trench is smaller, the following problems also occur. Namely, when an arsenic doped amorphous silicon film is embedded into the trench, voids occur which cause problems in later manufacturing steps.
Specifically, provide that a plurality of trench capacitors are formed and elements are isolated in a region including the two trenches by Shallow Trench Isolation (to be described later and referred to as STI hereinafter). In this case, the arsenic doped amorphous silicon film present in the above-stated region is etched away and thermal oxidation is conducted onto the entire portion. During the etching process, voids occur within the arsenic doped amorphous silicon film and the portions of the arsenic doped amorphous silicon film where the voids appear are oxidized to thereby generate defects.
In the manufacturing process of semiconductor chips having trench structure, the number of steps is increasing to ensure necessary capacity. The increased number of steps needs to be reduced by adopting effective process.
Of Meanwhile, element isolation is conducted by using one of the local oxidation methods, i.e., LOCOS element isolation. According to the LOCOS element isolation, the oxide film bites into the element formation region, which phenomenon is called bird""s beak, and the effective area of the element formation region decreases. For that reason, the LOCOS element isolation is not effective for high integration purposes.
In view of the above, the STI has been widely used in recent years. The STI is the method by which a shallow groove serving as an element separation trench is formed on the surface of the substrate and the shallow trench is filled with the element isolation insulating film. Unlike the LOCOS element isolation, the STI does not cause a bird""s beak. Due to this, a decrease in the area of the element formation region is prevented, which is therefore suitable for high integration purposes.
The conventional STI has, however, the following problems. The trench of this type is formed by RIE, and uneven portions are generated on the inner surface of the trench.
As a result, the phenomenon that part of the channel of the MOS transistor cell is turned on earlier than the rest and that transistor characteristics thereby deteriorate. In addition, since it becomes difficult to embed a favorable shaped element isolation insulating film into the trench, defective element isolation occurs and reliability deteriorates.
It is therefore the first object of the present invention to provide a semiconductor device having a trench suitable for smaller-sized elements, and to provide a manufacturing method thereof.
It is the second object of the present invention to provide a method of manufacturing a semiconductor device wherein only the surface of a desired exposed silicon region is made smoother than those of other plural exposed silicon regions.
To attain the above-stated objects, a semiconductor device in the first aspect according to the present invention comprises:
a semiconductor substrate having a trench on a surface thereof; and
an embedding member embedding an interior of the trench therewith, and is characterized in that
while a section of the trench when cut by a first plane perpendicular to a direction of a depth of the trench is defined as a first section, and a section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to a bottom of the trench than the first plane is defined as a second section, an area of the first section is smaller than an area of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section.
A semiconductor device in the second aspect according to the present invention comprises:
a semiconductor substrate having a trench with an aspect ratio of 10 or more on a surface thereof; and
an embedding member embedding an interior of the trench therewith, and is characterized in that
while a section of the trench when cut by a first plane perpendicular to a direction of a depth of the trench at a position away from a bottom of the trench by a distance corresponding to ⅘ of the depth of the trench in a direction of the surface is defined as a first section and a section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench at a position away from the bottom of the trench by a distance corresponding to ⅕ of the depth of the trench in the direction of the surface is defined as a second section, a value obtained by dividing a major diameter of the second section by a minor diameter of the second section is smaller than 1.1 times of a value obtained by dividing a major diameter of the first section by a minor diameter of the first section.
To be specific, in the first and second aspects, the trench is, for example, the trench of a trench capacitor or an element separation groove.
If the present invention is applied to a trench capacitor having a collar insulating film, using a rectangular mask for etching the trench, the capacitor has the following features.
The sectional shape of the trench when cutting the trench by a plane parallel to the surface of the substrate is rectangular as in the case of the mask if the collar insulating film is present. The trench located deeper than the collar oxide film has a larger minimum radius of curvature and a smoother shape than in case the collar insulating film is present.
A semiconductor device in the third aspect according to the present invention comprises:
a semiconductor substrate having a trench on a surface thereof; and
an embedding member embedding an interior the trench therewith, and is characterized in that
when the trench is cut through a substantial center thereof, the semiconductor device has a vertically asymmetric sectional shape about the substantial center of the trench.
A semiconductor device manufacturing method in the fourth aspect according to the present invention comprises the steps of:
forming a trench on a surface of a semiconductor substrate;
deforming the trench by a thermal treatment under reduced pressure such that, while a section of the trench when cut by a first plane perpendicular to a direction of a depth of the trench is defined as a first section and a section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to a bottom of the trench than the first plane is defined as a second section, an area of the first section is smaller than an area of the second section and that a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section; and
embedding an interior of the trench with an embedding member.
A semiconductor device manufacturing method in the fifth aspect according to the present invention comprises the steps of:
forming a trench on a surface of a semiconductor substrate;
deforming the trench by a thermal treatment under reduced pressure such that, while a section of the trench when cut by a first plane perpendicular to a direction of a depth of the trench at a position away from a bottom of the trench by a distance corresponding to ⅘ of the depth of the trench in a direction of the surface is defined as a first section and a section of the trench when cut by a second plane perpendicular to a direction of the depth of the trench at a position away from the bottom of the trench by a distance corresponding to ⅕ of the depth of the trench in the direction of the surface is defined as a second section, a value obtained by diving a major diameter of the second section by a minor diameter of the second section is smaller than 1.1 times of a value obtained by dividing a major diameter of the first section by a minor diameter of the first section; and
embedding an interior of the trench with an embedding member.
The step of embedding the interior of the trench with the embedding member can include:
a step of forming an impurity defused layer, serving as a first capacitor electrode, on an inner surface of the trench by diffusing impurities into the inner surface of the trench; and
a step of embedding the interior of the trench with a second capacitor electrode through a capacitor insulating film.
In the semiconductor device manufacturing method in the fourth and fifth aspects, the impurity diffused layer is preferably formed by diffusing the impurities into the inner surface of the trench by a thermal treatment under the atmosphere of gas containing the impurities.
It is also preferable that thermal treatment under reduced pressure and the thermal treatment under the atmosphere of gas containing the impurities are continuously conducted in the same vacuum chamber.
The thermal treatment under reduced pressure is preferable conducted at a temperature of not lower than 850xc2x0 C. and not higher than 1200xc2x0 C., more preferably 1100xc2x0 C.
The thermal treatment under reduced pressure is preferably conducted under the gas atmosphere where the surface of the semiconductor substrate is reduced. Specifically, it is preferably conducted under the gas atmosphere where SiO2 is reduced.
Moreover, the thermal treatment under reduced pressure is conducted under the hydrogen atmosphere.
A semiconductor device manufacturing method in the sixth aspect according to the present invention comprises the steps of:
forming a first trench on a surface of a semiconductor substrate;
separating the first trench into a plurality of cells arranged to be distant from one another substantially along a center line of the first trench by a first thermal treatment under reduced pressure;
forming a second trench on the surface of the semiconductor substrate so as to include part of each of the plurality of cells;
smoothing an interior of the second trench by a second thermal treatment under the reduced pressure to thereby deform the second trench into a trench having a vertically asymmetric sectional shape about a substantial center line of the second trench; and
embedding the interior of the trenches with an embedding member.
In this case, the first thermal treatment is preferably conducted at a temperature of 1100xc2x0 C., more preferably 1200xc2x0 C. or higher.
The second thermal treatment is preferably conducted at a temperature of not lower than 850xc2x0 C. and not higher than 1200xc2x0 C., more preferably 1100xc2x0 C.
In addition, it is preferable that the surface of the substrate is flattened after the first thermal treatment and then the second trench is formed. Specifically, a semiconductor film is deposited on the entire surface and the surface of the semiconductor film is flattened by the thermal treatment under reduced pressure.
According to the study by the inventors of the present invention, it has been discovered that the shape of the trench formed on the surface of the substrate can be deformed into a shape suitable for smaller-sized elements by the thermal treatment under reduced pressure.
Namely, it has been discovered that angular portions of the trench, in particular, those at the bottom thereof can be rounded by the thermal treatment under reduced pressure. The deformation of the shape of the trench mentioned above makes it possible to relax the electric field concentration and to thereby improve the withstand voltage.
Furthermore, it has been discovered that uneven portions formed on the side surface of the trench during etching can be eliminated by the thermal treatment under reduced pressure, thereby providing a smoother side surface of the trench.
The effect of relaxing the electric field concentration can provide improved withstand voltage even if the trench is smaller and smaller.
Moreover, the trench is usually formed by etching such as RIE and is tapered as the etching progresses. When thermal treatment under reduced pressure was conducted onto a semiconductor substrate having a trench of this type, the inventors has discovered the following.
The tapered trench could be deformed such that the section area of the trench at a position close to its bottom is larger than that at a position distant from the bottom. The deformation of the shape as stated above makes it possible to improve the embedding shape of the embedding member. If so, elements such as a trench capacitor can be made smaller in size.
The first aspect according to the present invention relates to the characteristic deformation of the shape of the trench. FIGS. 33A through 33C typically show the trench of the present invention. FIG. 33A is the sectional view of the trench including the central axis in the depth direction of the trench. (The convex portion at the bottom thereof is not illustrated in FIG. 33A.) The plane shape at a section perpendicular to the central axis of the trench is elliptical in upper portion (FIG. 33B) and the lower portion (FIG. 33C) of the trench. If the major diameter of the upper elliptical shape is defined as Dlb and the minor diameter thereof as Dsb, and the major diameter of the lower elliptical shape is defined as Dlc and the minor diameter thereof as Dsc, the trench of the present invention satisfies the relationship expressed by the following formula:
(Dlc/Dsc)/(Dlb/Dsb) greater than 1.1xe2x80x83xe2x80x83(1)
This indicates that the elliptical shape is closer to a complete round at the bottom of the trench.
FIG. 34A typically shows the section of the trench formed by using a rectangular exposure mask and the RIE. Even if the rectangular exposure mask is used, an etching mask having a elliptical opening portion is formed due to uneven exposure with the current exposure technique (FIG. 34B).
According to the RIE using this etching mask, the initial (or upper) portion of the substrate is etched to an elliptical shape (FIG. 34C). However, if etched deeper, the dependency of the substrate on surface orientation appears and the substrate is etched to a rectangular shape (FIG. 34D).
Thus, the trench formed by the RIE and having an aspect ratio of 10 or more has an elliptical sectional shape at the upper portion (⅘ of the depth of the trench from the bottom) and a rectangular sectional shape at the lower portion (⅕ of the depth of the trench from the bottom).
According to the experiments made by the inventors of the present invention, a minimum radius of curvature of the lower portion of the trench was 25 nm or more. When the thermal treatment under reduced pressure according to the present invention was conducted, by contrast, it was discovered that a minimum radius of curvature of the lower portion of the trench was 150 nm or more. In other words, it has been confirmed that the thermal treatment under reduced pressure makes it possible to round the sharpest angular portions and to deform the shape of the trench into a shape with which the electric field concentration hardly occurs.
FIGS. 34A through 34D show states prior to the thermal treatment under reduced pressure. It is noted that after thermal treatment is conducted, the states are as shown in FIGS. 33A through 33C.
The fourth and fifth aspects according to the present invention are a method of forming a trench capacitor using the trench in the first and second aspects according to the present invention as the trench of the trench capacitor.
In this case, an impurity diffused layer (or a first capacitor electrode) is preferably formed by the thermal treatment under the atmosphere of gas containing impurities as a dopant, i.e., by impurity diffusion from the vapor phase.
In this method stated above, impurities can be always supplied to the inner surface of the trench from the vapor phase. Due to this, even if the diameter of the trench is small (or the aspect ratio of the trench is high), an impurity diffused layer having necessary impurity concentration can be easily formed.
The thermal treatment under reduced pressure is preferably conducted at a temperature of not lower than 850xc2x0 C. and not higher than 1200xc2x0 C., more preferably 1100xc2x0 C. The reason is, in case of the silicon substrate, the surface migration of silicon occurs under reduced pressure at 850xc2x0 C. or higher and the trench is separated into upper and lower portions under reduced pressure at a temperature higher than 1200xc2x0 C., or 1100xc2x0 C. under some conditions.
In addition, the thermal treatment under reduced pressure is preferably conducted under the reducing gas atmosphere. The reason is that, if the semiconductor substrate is oxidized and an oxide film is formed on the surface of the substrate, then the migration phenomenon of constituent elements of the semiconductor substrate is hampered and the deformation of the shape of the trench is thereby suppressed.
Moreover, the thermal treatment under reduced pressure and that under the atmosphere of gas containing impurities as a dopant are preferably conducted under vacuum in a continuous manner.
The reason is that the native oxide film formed on the surface of the substrate is removed while the thermal treatment under reduced pressure is being conducted. If the thermal treatment is conducted under the atmosphere of gas containing impurities as a dopant while maintaining the state in which the native oxide film is removed, it is possible to decrease the number of manufacturing steps without the need to add another step for removing the native oxide film.
Additionally, if the trench has an asymmetric sectional shape as in the case of the present invention, the surface area of the asymmetric sectional shape is larger than that of the symmetric sectional shape under the condition of the same depth. Due to this, if such an asymmetric trench is applied to, for example, the trench of a trench capacitor, necessary capacity can be ensured even if elements are made smaller in size.
A semiconductor device manufacturing method in the seventh aspect according to the present invention comprises the steps of:
forming a first silicon region and a second silicon region on a silicon substrate, a surface of each of the first and the second silicon region being exposed;
forming a protection film consisting of carbon on the first silicon region; and
making the surface of the second silicon region smoother by a thermal treatment under reduced pressure.
The step of forming the first silicon region and the second silicon region preferably includes a step of forming a polycrystalline silicon gate electrode as the first silicon region on the silicon substrate and forming a trench as the second silicon region on the surface of the silicon substrate.
The step of forming the protection film preferably includes:
step of forming a base film on the second silicon region;
a step of forming the protection film on an entire surface; and
a step of removing the protection film on the second silicon region by removing the base film.
The step of making the surface of the second silicon region smoother preferably includes a step of removing the base film by the thermal treatment.
The step of making the surface of the second silicon region smoother preferably includes a step of conducting the thermal treatment under reduced pressure in a reducing gas atmosphere.
The study made by the inventors of the present invention has discovered that carbon does hardly react to the silicon film and is attached to the surface of the silicon surface to thereby form a film and that the film formed by the attachment of the carbon to the surface can be selectively removed without difficulty. It has been also discovered that such carbon characteristics are not related to crystalline states of the silicon film, that is, monocrystalline, polycrystalline and amorphous states.
According to the seventh aspect of the present invention, therefore, the thermal treatment under reduced pressure enables only the surface of the a desired silicon region (the second silicon region) to be made smoother and the unnecessary protection film to be easily removed in the later steps.
If, for example, the surface of the polycrystalline silicon gate electrode and the surface of the trench are selected as the first silicon region and the second silicon region, respectively, the deformation of the shape of the polycrystalline silicon gate electrode can be prevented when the surface of the trench is smoothed by the thermal treatment under reduced pressure.
If an element isolation groove is selected as the trench, it is possible to prevent the phenomenon that part of the channel of a transistor is turned on earlier than the rest and to prevent defective element isolation. If the trench of the trench capacitor is selected as the trench, it is possible to prevent the withstand voltage of the capacitor insulating film from lowering.
Further, to form a protection film on the first silicon region selectively, the protection film on the second silicon region may be removed by first forming a base film on the second silicon region, next forming the protection film on the entire surface and finally removing the base film.
In this case, for purposes of reducing the number of steps, it is preferable that not only the base film on the second silicon region is removed but also the surface of the exposed second silicon region is made smoother by the thermal treatment under reduced pressure.
If so, the base film is preferably a thin oxide film. This is because a thin oxide film can be easily removed if the thermal treatment under reduced pressure, high temperature and hydrogen atmosphere is selected.
It is also preferable that the thermal treatment under reduced pressure is conducted under the reducing gas atmosphere. The reason is that the oxidation of the second silicon region is suppressed under the reducing gas atmosphere while the surface migration which provides the smoother surface of the second silicon region is not suppressed.
Furthermore, the unnecessary protection film after the thermal treatment can be easily removed with a solution mixture of, for example, sulfuric acid and hydrogen peroxide.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinbefore.